先进封装技术因其在延续摩尔定律，促进芯片性能提升方面的重要价值，近来成为IDM与OSAT企业共同关注的焦点。随着技术演进，各应用领域对采用先进封装的芯片成品，也呈现出多元化需求。

作为从业者，会如何看待先进封装的发展趋势？对不同先进封装技术的现状和发展又有怎样的见解？日前，长电科技首席技术长李春兴（Lee Choon Heung）先生，与美国Semiconductor Engineering网站进行了一次涉及半导体市场前景、摩尔定律、小芯片（Chiplet）、扇出型封装（Fan-out）等市场与行业热点的对话。

*Semiconductor Engineering网站的文章均来自具有深厚行业知识和经验的独立记者及专业工程师，旨在让读者深入了解有关半导体设计、测试、验证、集成和制造的市场动态与行业洞察。

李春兴  Lee Choon Heung

李春兴博士自2019年5月17日起出任长电科技首席技术长，拥有美国凯斯西储大学理论固体物理博士学位。

李春兴博士在半导体领域拥有20多年的工作经验，曾任Amkor Technology首席技术官、全球制造业务执行副总裁和Amkor韩国总裁。李博士撰写有各种封装技术相关课题的研究论文，拥有韩国专利38项，美国专利21项。

以下为对话摘录（SE=Semiconductor Engineering）：

SE：我们现在处于半导体周期的哪个阶段？

李春兴：2020 年整个半导体行业的增长率约为10%。到2021年，预计将增长将达到24%左右。今年较高的增长可以归因于新冠疫情的影响——大家都在购买各种电子设备，保持与外界的连接。如果对2022年做个预测，增长率可能只有个位数字。尽管如此，就半导体复合年增长率或CAGR而言，不考虑通货膨胀或其它因素，只是看半导体市场本身，这个（增长）仍然是很稳定的。只有2021年比较特殊。

Lee: If you look at 2020, it was around 10% growth in the overall semiconductor industry. Then, in 2021, it is expected to be about 24% growth. This can be attributed to the Covid situation. Everyone is buying all types of systems to connect with each other. But if you look at 2022, it looks like single-digit kind of numbers. Still, in terms of the semiconductor compound annual growth rate, or CAGR, it looks solid. It’s just that 2021 is really exceptional. I’m not taking in account the other parameters like inflation or other factors. If you look at the pure semiconductor market, it looks okay.

SE：芯片市场有哪些主要驱动因素？

李春兴：汽车行业是推动力之一。尽管存在芯片短缺，但汽车行业仍在增长，电动汽车、自动驾驶等正在推动（芯片市场）增长。现在汽车行业一直关注安全性，与安全相关的功能，例如传感器或者高级驾驶辅助系统（Advanced Driving Assistance System, ADAS），都是芯片在汽车行业应用增长的推动力。许多汽车产品中，每辆车的电子设备费用达到600美元，而且汽车中的电子设备还将增加。然后还有5G相关应用，比如“车与车”交互，这推动了高端信息应用市场。这些技术现在仍处于早期阶段，不过每个汽车制造商都在关注这一领域。

Lee: Automotive is one of the driving forces. Even though there are chip shortages here, automotive is still growing. Then, electric vehicles, autonomous driving and so on are fueling the growth. And for some time, the automotive industry has been focusing on safety. You have safety-related features in cars like sensors or even ADAS. That’s a big driver in automotive. The electronic content in many cars is around \$600 per car. It’s going up from there. Electronic content in cars will increase. Then, for 5G-related applications, you have car-to-car or vehicle-to-vehicle (V2V) communications. That’s driving the high-end infotainment market. This technology is still in the early stages. Every carmaker is looking at that.

SE：还有什么在推动半导体市场，对封装有什么影响？

李春兴：另一个驱动因素是人工智能。人工智能涉及高性能计算（HPC）。我们看到与AI或HPC应用相关的FcBGA需求很大。这其中还包括2.5D、3D或高密度扇出型封装产品。云计算是人工智能应用的一个大市场，数据中心行业的需求持续提高，他们需要更好的产品以提高效率并降低运营成本。这部分的市场规模正在以惊人的速度增长。

Lee: Another driver is AI. AI involves high-performance computing (HPC). We are seeing a lot of demand for flip-chip BGA, which is linked to AI or HPC applications. That also includes 2.5D, 3D, or high-density fan-out. The cloud is a big market for AI. The adoption rate here in data centers continues to increase. Data centers are also enhancing their efficiency and reducing their operational costs. The amount of data is increasing at a tremendous rate.

SE：那 5G 呢？

李春兴：5G是通信领域的重要部分，但5G尚处于早期阶段，还没有进入成熟阶段。由于新冠疫情，一些国家推迟或放慢了5G的基础设施建设，预计明年5G基础设施建设将提速。手机制造商也非常重视将5G功能纳入其智能手机产品。对于OSAT企业，5G是一个很大的驱动力，我们也一直在为5G应用部署相关生产设施，尤其是系统级封装 （SiP）。另外5G还涉及AiP——即封装天线这种新型的封装技术。

Lee: In the communication sector, there is 5G. But 5G is not in the mature stages yet. It’s still in the early stages. Because of the Covid situation, some countries delayed or slowed their infrastructure buildouts of 5G. Next year, many will focus on bringing up the infrastructure in 5G. Every phone maker is serious about incorporating 5G content in their smartphones. For the OSAT market, 5G is a big driver. We have been expanding our capacity and putting the infrastructure in place for 5G demand, especially for system-in-package (SiP). In 5G, you also have AiP, or antenna-in-package, as a new feature in a package.

SE：您如何看待摩尔定律？

李春兴：摩尔定律所说的“芯片密度每两年翻一倍”这种情况很难继续发生了，它并不是彻底失效，但正在放缓。

Lee: Moore’s Law, by definition, involves doubling the chip density every two years. But that isn’t happening anymore. It’s slowing down. But we can look at this from a different aspect. We’ve heard about a 40% performance increase at each node. But in terms of its original definition, Moore’s Law isn’t really catching up. It’s not really dead. It is slowing down.

SE：此时此刻一些传统的技术正在蓬勃发展。成熟的200mm晶圆需求很大，是这样吗？

李春兴：说起来很神奇，即使在OSAT中，8英寸晶圆级的需求也是巨大的，在某些情况下还要大于12英寸。正如我们所讨论的，汽车行业是这里的一个重要驱动因素，另外还有工业物联网，他们对模拟器件的需求是巨大的。在涉及电动汽车等技术时，功率变得越来越重要。

Lee: It’s amazing. Even in the OSATs, the 8-inch wafer-level demand is huge. In some cases, it’s bigger than 12-inch. It’s an inflection of the industrial transformation. As we discussed, automotive is a big driver here. Then, we have industrial IoT. Demand for analog is huge, even in automotive. Power is becoming more critical when it comes to technologies like electric vehicles.

SE：芯片封装并不是新事物，但几年前它比较边缘，只是封装和保护芯片。然而最近封装在所有行业中变得越来越重要。发生了什么变化？

李春兴：智能手机市场推动了最初的变化。智能手机中嵌入了更多的功能，如果观察3G、4G和5G的演进，就会发现智能手机在同一主板区域内集成了更多芯片，对SiP封装的需求越来越多。随着从3G到4G以及从4G到5G的演进，芯片的大小尺寸（长、宽、高）成为智能手机的关键参数。另一个驱动因素是高性能计算领域。 在先进封封装中，扇出型封装和RDL技术成为封装模式中的基准。

Lee: The smartphone market drove some of the first changes. In a sense, there are more functions embedded in smartphones. If you look at the 3G, 4G, and 5G evolution, the smartphone incorporates more dies in the same motherboard area. That drove everything toward a SiP-type of format. The x, y, and z form factor became a critical parameter for the smartphone, along with evolution from 3G to 4G and 4G to 5G. Another driver is the high-performance computing area. Then, with (TSMC’s) InFO, RDL technology became a baseline for a packaging format in advanced packaging.

SE：小芯片（Chiplets）是一个热门话题，因为它可以从模块化功能中进行选择。您对此怎么看？

李春兴：很多人都在谈论小芯片。在小芯片出现之前，人们就在想：“我希望在封装架构中拥有不同功能的SoC，而不是传统的单片 SoC。”这是影响封装发展的一个变化。从某种意义上说，这种先进的封装，或先进的产品需要高密度互连。因此，在这种情况下，封装本身不再只是封装单个芯片。在更先进的封装中，必须考虑布局、芯片和封装的互联以及如何布线。这些正在成为元件制造商设计芯片时要考虑的一些基本参数。小芯片封装现已进入市场。这个概念原先来自IDM或元件制造商——他们将封装视为产品性能的一部分。

Lee: Everyone is talking about chiplets. Even before chiplets, people were thinking, ‘I would like to have a different and functional SoC in a package-like architecture instead of a traditional monolithic SoC.’ That’s another change that impacts packaging. In a sense, this kind of advanced package, or advanced product, requires high-density interconnects. So in that context, packaging itself is no longer just a single die in a package with encapsulation. In more advanced packaging, you have to think about the layout, the interactions with the chip and the package, and how to route these layers. These are becoming some of the fundamental parameters to think about when device makers design their own chips. Chiplets are already in the market. This concept is coming from the IDMs or the device makers. They look at the package as part of their product performance and product launch.

SE：能再多谈论一些您对小芯片的看法吗？

李春兴：从系统的角度来看，Chiplet是一种多芯片架构。从OSAT的角度来看，问题在于如何真正在封装中优化布局以获得更佳性能。在某些方面，小芯片概念是由元件制造商去定义的，他们设想了拆分SoC的想法。模拟(器件)可能是一个节点。当制造商拥有16nm/14nm/7nm的IP时，需要进一步探索的问题在于如何获得更好的晶圆产量并节省费用。总之从业者正在考虑如何从单片SoC设计中融入多种功能。

Lee: From a system point of view, a chiplet is a multi-die architecture. From an OSAT’s perspective, the question is how do you really optimize the layout to get the optimal performance or maximum performance in the package. In some respects, the definition of a chiplet is being driven by the device makers. The device guys envision the idea of breaking up an SoC. Analog would be at one node. Then, you might have 16/14nm/7nm IP. The argument is you get better wafer yield and save money. They are thinking about how to disaggregate the discrete functions out of a monolithic SoC design. Right now, AMD is very active in chiplets. They are working with TSMC on SoIC. They have already implemented this architecture and made improvements to the performance. AMD has fully utilized this advanced packaging concept.

SE：2015年，长电科技收购了星科金朋。现在长电科技能提供丰富的封装和技术服务组合，业务遍及全球。接下来有什么计划？

李春兴：长电科技管理层已经提出了未来几年的投入规划。作为OSAT的领先企业，我们会对技术和制造能力进行持续投入。

Lee: We have an expansion plan. JCET management has approved a sizable CapEx for the years to come, and we have prepared the space in order to expand the capacity. As a leading figure in the OSAT market, we rely on the continuous investment in technology and manufacturing capacity.

SE：我们已经看到很多晶圆厂扩大了他们的封装生产能力，例如英特尔、台积电和三星。您对此怎么看？

李春兴：在很多方面，晶圆厂更关注先进的封装形式，这是晶圆厂的前端流程。我们也会专注于自身所长，晶圆级扇出封装就是一个例子。我们正致力于2μm x 2μm线间距的技术开发，从而获得更高性能和更高良率。

Lee: In many ways, the foundries focus more on advanced packaging formats, something like SoIC from TSMC. That’s a foundry front-end process. We want to focus on our own capabilities. Wafer-level fan-out packaging is an example. We are working on 2μm x 2μm with high performance and good yields.

SE：让我们谈谈其它封装类型，比如焊线。这仍然是一项大生意对吧？

李春兴：就半导体的产量而言，焊线（封装）约占80%。我们可以看看焊线封装技术的演变，在我们的工厂中，我们可以处理一个芯片中包含2,500根焊线的封装。焊线的优势在于成本和可靠性，引线框封装（Leadframe-based）及LGA封装的价格比较低廉，它的需求量很大，我们也投入很多资源来扩大这类产能。

Lee: In terms of the number of units in semiconductors, wire bonding takes up like 80%. Take a look at the evolution at wire bonding technology. In our factory, we’re handling something like 2,500 wires in a package. One factor in wire bonding is cost. The other one is reliability. Leadframe-based or LGA packages are inexpensive. It’s a two-layer organic substrate. But it’s a huge number of units. We have spent a lot of money to expand the capacity here.

SE：扇出式封装越来越受欢迎，长电科技对这种技术并不陌生。你们在嵌入式晶圆级球栅阵列（eWLB）有丰富的经验对吗？

李春兴： 长电科技的新加坡工厂是早期的eWLB封装的参与者之一。我们从一开始就使用英飞凌的许可启动了eWLB。扇出是一个分散的细分市场，我们也正在尝试进入不同的细分市场。eWLB适合小批量、多元化的市场，在性能表现方面也很有价值，且具有封装尺寸小的优势。我们仍在关注eWLB市场的增长趋势。

Lee: JCET’s Singapore operation was one of the early entrants in eWLB. They started eWLB from the very beginning with a license from Infineon. But fan-out is a fragmented market segment. We are trying to go into different market segments here. It’s a good fit for the low-volume, high-mix market, but it’s still valuable in terms of performance. It has some advantages with its x, y, and z form factors. Right now, we see the growth in eWLB. That’s the low-end of fan-out.

SE：长电科技最近凭借一项名为XDFOI™的技术进入了高密度扇出市场。能否介绍一下？

李春兴：长电科技在今年发布了XDFOI™。这基本上是一种RDL优先，高密度扇出技术。我们正在开发具有2μm线宽和间距的RDL。相比之下，eWLB是10μm/15μm的线宽和间距。我们正在进入高密度扇出市场，为客户提供新的选择。许多人都看到了不需要硅中介层的扇出型封装的价值。因此，长电科技计划为客户提供这种高端扇出产品。

Lee: JCET recently announced plans with XDFOI. This is basically a chip-last, RDL-first, high-density fan-out technology. We are developing RDLs with 2μm line and space. In contrast, eWLB is 10μm/15μm line and space. We are moving into the high-density fan-out market to provide new options for customers. Many see a value proposition using fan-out without the silicon interposer. So we plan to have a high-end fan-out offering from JCET.

SE：一些公司正在提供可以支持高带宽内存（HBM）内存和其它复杂元件的高密度扇出产品，您对此怎么看？

李春兴：当然，我们也有需要不同内存配置的高密度扇出产品的客户。

Lee: Definitely, we have customers for our high-density fan-out with different memory configurations.

SE：高密度封装的线间距是怎样的趋势？

李春兴：目前，4μm x 4μm线间距已经量产（HVM），2μm x 2μm线间距也正在向量产迈进。虽然步进式光刻机可以处理1μm x 1μm线间距，但量产良率仍存在挑战。如果不能解决量产良率，就没有任何价值，所以我们还是更关注高良率。相比之下，采用四层RDL和2μm x 2μm线间距，良率要高得多。

Lee: Right now, 4μm x 4μm is used in high-volume manufacturing (HVM), and 2μm by 2μm is moving to HVM. In regard to the resolutions, steppers can handle 1μm x 1μm. But the challenge is to achieve the yields. Without achieving the yields, there is no value at all. Our focus is to achieve high yield. High yields translate well above 99% with a four-layer RDL and a 2μm line and space.

SE：你们的光刻流程是使用传统步进式光刻机还是直写式？

李春兴：我们使用步进式光刻机。我们正在使用先进的系统，可以处理2μm x 2μm线间距。

Lee: We use the conventional stepper. We are using an advanced system. We can do 2μm x 2μm.

SE：扇出的最大挑战是芯片移位和翘曲，对吗？

李春兴：在2umx2um线间距这样的尺寸下，芯片移位并不是主要问题。当达到这么高的集成度时，particle才是最大的挑战。

Lee: Die shift isn’t really the major issue in 2μm x 2μm. When you go down to these fine lines and spaces, particles are the killer in the process. Particles are the biggest challenge.

SE：这意味着您需要更多的检查手段？

李：没错。在像10μm线间距这样普通RDL中，底切是1μm。但到了2μm，底切是一个很大的挑战。对比10μm x 10μm与2μm x 2μm，挑战性完全不同。因此，需要非常谨慎地对过程进行优化。

Lee: Exactly. In normal RDLs like 10μm line and space, the undercut is 1μm. If you have 2μm line and space, the undercut is a big challenge. It’s a totally different challenge when you compare 10μm x 10μm versus 2μm x 2μm. So you need to be very cautious about fine tuning the process.

SE：您对面板形式的扇出（panel-level fan-out）有何看法？

李：四五年前我并不乐观。问题出在面板格式方面没有标准，设备也不够成熟。今天这方面的驱动力又来自哪里？面板形式封装要与晶圆级做对比——我不是在谈论市场本身，也不是在谈论哪些客户会采用它。从成本的角度来看，如果一条12英寸线已经折旧了，你想开启一个面板生产线，就必须考虑折旧问题。然后，新产品导入时，需要在面板上进行完整的认证，这是一种不同于晶圆级的调试过程。在一次会议上，我对晶圆级与面板级进行了比较。以7μm x 7μm的编解码芯片为例，假设智能手机的销量约为14亿部，那么就需要14亿个此类封装。那么假设你拥有每月生产20,000个面板的产能，而只需要10,000平方米的面板就可以支撑这14亿个产品。

Lee: Four or five years ago, I was very pessimistic. The issue is that there are no standards in terms of panel formats. At the time, there were equipment issues. There was a lack of maturity there. What’s the driving force today? The motivation of panel-level processing was cost compared wafer level. I’m not talking about the market itself, or which customers will adopt it. From the cost standpoint, a 12-inch line is already depreciated. If you want to start a panel line, you have to think about depreciation. That’s one issue. Then, whenever you have a new device, you need to undergo a full qualification process on panel. It’s a different qualification process from a wafer-level one. In one conference, I made the comparison between wafer-level versus panel-level. Take a codec-like chip at 7μm x 7μm, for example. Let’s say smartphone sales are roughly 1.4 billion. You need 1.4 billion units of this package for each phone as one example. Then, you might have a facility with 20,000 panels per month. Even a 10,000 square meter panel can handle 1.4 billion units.

SE：您对混合键合有什么想法？

李春兴：混合键合在我们的计划蓝图里，这与凸块技术有关。索尼一直在使用混合键合，将之用于CMOS图像传感器。现在，很多人都在研究混合键合，它可以实现高密度的芯片到芯片键合，基本上是铜对铜的粘合。在混合键合中，不用铜凸块上加入银锡合金罩，它只是铜对铜，晶圆对晶圆键合的另一种互连过程。

Lee: We have hybrid bonding on the roadmap. This has something to do with the bump pitch. Sony has been using hybrid bonding. Sony has been doing this a long time for CMOS image sensors. Now, everyone is working on hybrid bonding. It enables high-density die-to-die bonding. It’s basically copper-to-copper bonding. In hybrid bonding, you are not extending copper bumps, which consists of a tin-silver cap on copper. It’s just copper-to-copper. It’s a different interconnection process of wafer-to-wafer bonding.

SE：在现在的先进封装中，芯片使用铜微凸块堆叠和粘合。最先进的微凸块采用40μm间距，相当于20μm至25μm凸块尺寸，管芯上相邻凸块之间的间距为15μm。业界正在致力于开发超过40μm的更细间距，以实现更多 I/O。您对此怎么看？

李春兴：现在，40μm是量产中的常见凸块间距。我们也正在致力于10μm，尝试在这方面建立我们的工程数据。如果客户希望他们产品的芯片到芯片键合间距降低到10μm，我们也能够处理。但是当涉及到小于1μm的间距时，就会变得非常有挑战性。通常这个挑战会由晶圆厂去应对。一般来说OSAT的能力就只到10μm。

Lee: Now, 40μm is the common bump pitch for HVM. For 10μm, we are working on that. We are trying to build up our engineering data here. If customers want to go down to 10μm pitches for their own devices that involves die-to-die bonding, we will be capable of handling this. But when it comes to less than 1μm-like pitch, this is where it gets challenging. This is a foundry-like process. Generally, the capabilities for OSATs is down to 10μm, maybe past that pitch.

SE：您有关注热压粘合吗？

李春兴：没有。我们实际上是采用激光辅助键合（LAB）。LAB将激光束照射到芯片上，其中凸点尖端是Sn或SnAg，用于将它们连接到基板。这提供了比热压更高的UPH（每小时产出）和更强大的互连，它的残余应力比回流焊（MR）小得多。

Lee: No. We actually are employing laser-assisted bonding (LAB) instead. Laser-assisted bonding shines a laser beam to the chips, where the bump tips are Sn or SnAg. LAB is used to connect them to the substrate. This gives a higher UPH (units per hour) and more robust interconnection than thermocompression. It provides much less residual stress than MR (mass reflow).

SE：最后，有什么让你非常担心的事吗？

李春兴：在某些情况下，OSAT与晶圆厂在封装技术上会有重叠，这使得OSAT的业务在投资支出和投资回报率方面有更多不确定性，另外也包括购置自动化专用的制造基础设施时也可能出现竞争。

Lee: In some cases, packaging technologies often overlapped with the foundries in terms of capabilities, making the business situation more dynamic in the OSAT environment in terms of CapEx investment and ROI, as well as having a dedicated manufacturing infrastructure with automation.